Study of Reactive Ion Etching Process to Fabricate Reliable Via-Hole Ground Connections in GaAs MMICs

In this study we have investigated the effect of starting GaAs semi-insulating substrate surface (polished / unpolished), type of mask used (photoresist / Nickel) and RIE parameters (pressure and power) on the surface smoothness/morphology of the etched via-walls and resultant etch profiles with CCl2F2 / CCl4 gas chemistry. The ultimate aim of the study has been to develop a reliable via-hole ground contact for MMICs upto 40GHz frequency range. Via-hole etching process in GaAs has been studied using reactive ion etching with CCl2F2/CCl4 chemistry. The effect of starting substrate surface, type of mask used and RIE process parameters viz. pressure and power on the surface morphology of etched wall and etch profile has been investigated. Extensive SEM characterization was carried out to study the surface morphology, etch depth and etch profiles. The starting polished surface with photoresist mask was found to give better surface morphology of the etched wall. The surface smoothness improved with increase in pressure but at the cost of anisotropy. Increase in power resulted in anisotropic etch profiles but with poor surface morphology. RIE process with 50 mTorr pressure and 200W power were found to give desired profile and acceptable surface smoothness. Finally these process parameters with photoresist mask and polished starting surface were implemented in MMIC via-process and MMICs with 50μm dia., 100μm deep, low resistance (~0.4Ω) via hole grounds were fabricated with yield > 80%. The inductance offered by these via’s was ~ 25 ± 5 pH, well within acceptable limits. EXPERIMENTAL Completely frontside processed, 650 μm thick, 3” GaAs wafers were coated with photoresist on front and mounted on sapphire carrier wafers with wax, frontside facing down. The backside of the wafers was thinned down to 100±5 μm thickness. Then via-hole pattern of 50 μm dia. holes were aligned and patterned using BSA lithography on the mounted wafer, either with 30 μm positive photoresist AZ9260 or 3000 A of Ni. An oxygen plasma descum step prior to etching was utilized in order to remove any residual photoresist in the via hole which would contribute to the roughness of the etched surface. INTRODUCTION A backside via is an important element in GaAs MMICs. It provides electrically a low inductance grounding and at the same time serves as a heat sink. This step has proven to be one of the most difficult process associated with MMIC fabrication. It consists of via-hole etching and thin film metallization. Etching is performed from backside of the wafer to contact grounding pads on the front side[1-3]. Dry etching is preferred over wet etching because of its superior uniformity and dimensional control. The most common dry etching technique for etching via holes is reactive ion etching (RIE). Highdensity plasma etching techniques, such as electron cyclotron resonance (ECR) and inductively coupled plasma (ICP), have also been reported to give relatively higher etch rate and good anisotropy. Mainly chlorine based gases are used to etch III-V compounds and a number of chemistries have been reported including, BCl3/Cl2[4], SiCl4/Cl2[5] and CCl2F2[6]. Because via hole etching follows all other device fabrication processes, the process reliability and reproducibility are very important. The surface morphology and profile of the via are important not only for the inductance consideration but also for the success of backside metallization. The smooth morphology of the etched sidewalls provides reliable and good electrical contact with low resistance. Dry etching was performed in conventional parallel plate RIE. Wafers were placed on to the lower electrode to which 13.56MHz RF power was applied. The chamber was evacuated to a base pressure of 8e-6torr, by a turbomoleculer pump backed by a mechanical pump, before introducing the process gases into the chamber. The gas flow rates were regulated by mass flow controllers and chamber pressure was controlled by automatic throttle valve. The lower electrode temperature was kept at 30°C during the process to suppress the formation of less volatile compounds like GaF3 [7]. One wafer was etched at a time. After etching, photoresist/Ni mask was removed and front to backside contact was made through etched hole by seed metal deposition (Ti/Pt/Au, 3000A°) using RF sputtering and gold electroplating (5μm). The surface morphology, etch depth and etch profile of etched hole were determined by cleaving through feature and examining under SEM. RESULTS AND DISCUSSION I. Effect of starting substrate surface: Fig. 1 and fig. 2 show the SEM micrograph of etched surface (after 30 minutes of etching under identical conditions) of polished and unpolished starting substrate respectively at 5000X magnification. The starting polished surface of GaAs substrate leads to smooth morphology of the etched surface whereas the unpolished starting surface leads to rough etched surface with grass like structures and hence poor morphology. This has been attributed to more number of surface defects present on the unpolished surface giving rise to poor surface quality of etched area. It suggests that the defects on the surface play a major role in deciding the surface morphology of the etched surface. Rough morphology with grass like structures on unpolished surface indicates that the defective surface sites provide unequal etching sites causing uneven initial etching. The tip of the grass may be difficult to etch in an anisotropic etching condition. Thus the etching rate of tip is slower than the flat area and grass grows vertically as etching proceeds [8]. 3(a) 100mTorr